1. Technical Field
The invention relates to a method for arbitrated loop physical addressing (ALPA) for different hard disk drives (HDDs) in a Fiber Channel (FC) loop, and more particularly to a method for optimizing control circuit for FC HDDs in a system and control circuit for FC HDDs in a system based on their logic characteristics.
2. Related Art
In a typical example, each FC HDD needs a unique physical address in a FC loop for accessing the HDD correctly. A FC HDD has 7 address selection signals (SEL_ID[6:0]). These signals can make up 128 7-digit binary values (0-127), using 1 to indicate the logic high level and 0 to indicate the logic low level. Then, a HDD encodes the binary values to arbitrated loop physical addresses (ALPAs). According to SFF-8045 specification, the encoded ALPA of 126 (0b1111110) is “0”, and it acts as a reserved port. The ALPA of 127 (0b1111111) is a soft address. Therefore, an arbitrated FC loop supports only 126 (0-125) HDDs at the maximum, as is well known in this field.
All of address selection signals of the FC HDDs should be provided by mid-plane. Conventionally, one or more complex programmable logic devices (CPLDs) is used to provide a control signal for each address selection signal, and then the control signal will output the correct logic level (0 or 1) according to the system logic address so as to assign the correct ALPAs to the HDDs.
However, more and more HDDs are in one system to meet the technology development requirements. A system of 8 HDDs requires 56 control signals, a system of 16 HDDs requires 112 control signals, and a system of 48 HDDs requires up to 336 control signals. In this case, the number of CPLD chips or CPLD pins has to be increased to provide sufficient control signals, resulting in the increased cost and more space requirements for CPLDs on the mid-plane. Unfortunately, the available space on the mid-plane for CPLDs decreases when more HDD connectors are mounted and more thermal holes are required. Therefore, it is hard to place a big footprint CPLD or more CPLD chips on the mid-plane according to the conventional design.